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? semiconductor components industries, llc, 2016 february, 2016 ? rev. 3 1 publication order number: ncv7342/d ncv7342 high speed low power can transceiver description the ncv7342 can transceiver is the interface between a controller area network (can) protocol controller and the physical bus and may be used in both 12 v and 24 v systems. the transceiver provides differential transmit capability to the bus and differential receive capability to the can controller. the ncv7342 is an addition to the can high?speed transceiver family complementing ncv734x can stand?alone transceivers and previous generations such as amis42665, amis3066x, etc. due to the wide common?mode voltage range of the receiver inputs and other design features, the ncv7342 is able to reach outstanding levels of electromagnetic susceptibility (ems). similarly, extremely low electromagnetic emission (eme) is achieved by the excellent matching of the output signals. features ? compatible with the iso 1 1898?2, iso 11898?5 standards ? high speed (up to 1 mbps) ? v io pin on ncv7342?3 version allowing direct interfacing with 3 v to 5 v microcontrollers ? v split pin on ncv7342?0 version for bus common mode stabilization ? very low current consumption in standby mode with wake?up via the bus ? excellent electromagnetic susceptibility (ems) level over full frequency range. very low electromagnetic emissions (eme) low eme also without common mode (cm) choke ? bus pins protected against >15 kv system esd pulses ? transmit data (txd) dominant t ime?out function ? bus dominant time?out function in standby mode ? under all supply condition the chip behaves predictably ? no disturbance of the bus lines with an unpowered node ? thermal protection ? bus pins protected against transients in an automotive environment ? bus pins short circuit proof to supply voltage and ground ? these are pb?free devices quality ? wettable flank package for enhanced optical inspection ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable typical applications ? automotive ? industrial networks www. onsemi.com (top views) 5 6 7 8 1 2 3 4 txd rxd stb gnd canl see detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ordering information v cc v split (?0) v io (?3) canh pin assignments marking diagrams 1 8 soic?8 d suffix case 751az nv7342?x= specific device code x = 0 or 3 a = assembly location l = wafer lot y = year w = work week = pb?free package nv7342?x alyw 1 8 nv7342?x alyw (note: microdot may be in either location) nv7342?x alyw 1 dfn8 mw suffix case 506cs 1 stb canl v io canh txd rxd gnd v cc 1 2 3 4 5 6 7 8 ep flag
ncv7342 www. onsemi.com 2 table 1. key technical characteristics and operating ranges symbol parameter conditions min typ max unit v cc power supply voltage 4.5 5.5 v v uvvcc undervoltage detection voltage on pin v cc (ncv7342?3 only) 3.5 4.5 v i cc supply current dominant; v txd = 0 v recessive; v txd = v io 75 10 ma i ccs supply current in standby mode including v io current t j 100 c, (note 1) 15 a v canh dc voltage at pin canh 0 < v cc < 5.5 v; no time limit ?50 +50 v v canl dc voltage at pin canl 0 < v cc < 5.5 v; no time limit ?50 +50 v v canh,l dc voltage between canh and canl pin 0 < v cc < 5.5 v ?50 +50 v v esd electrostatic discharge voltage iec 61000?4?2 at pins canh and canl ?15 15 kv v o(dif)(bus_dom) differential bus output voltage in dominant state 45 < r lt < 65 1.5 3 v cm?range input common?mode range for comparator guaranteed differential receiver threshold and leakage current ?35 +35 v c load load capacitance on ic outputs 15 pf t pd_dr propagation delay txd to rxd dominant to recessive transition see figure 8 c i = 100 pf between canh to canl, c rxd = 15 pf 50 100 230 ns t pd_rd propagation delay txd to rxd recessive to dominant transition see figure 8 c i = 100 pf between canh to canl, c rxd = 15 pf 50 120 230 ns t j junction temperature ?40 150 c 1. not tested in production. guaranteed by design and prototype evaluation.
ncv7342 www. onsemi.com 3 block diagrams mode & wake?up control wake?up filter stb gnd rxd 2 3 7 6 comp comp 5 timer txd 1 driver control thermal shutdown 8 4 canh canl ncv7342?0 figure 1. ncv7342?0 block diagram rb 20121109 v split v cc v cc v cc v cc v split
ncv7342 www. onsemi.com 4 mode & wake?up control wake?up filter stb gnd rxd 2 3 7 6 comp comp 5 timer txd 1 driver control thermal shutdown 8 4 canh canl ncv7342?3 figure 2. ncv7342?3 block diagram rb 20121109 v cc v io v io v io
ncv7342 www. onsemi.com 5 typical application ncv7342?3 stb rxd txd 1 4 micro controller gnd vbat 5v?reg gnd 2 5 8 canh canl 3 6 7 can bus 3v?reg rb20120816 r lt = 60 r lt = 60 figure 3. application diagram ncv7342?3 ncv7342?0 stb rxd txd 1 4 micro controller gnd vbat 5v?reg in out gnd 2 3 8 canh canl 5 6 7 can bus rb20120816 v split r lt = 60 r lt = 60 c lt = 4.7 nf figure 4. application diagram ncv7342?0 c lt = 4.7 nf v io v io v cc v cc v cc table 2. pin function description pin name description 1 txd transmit data input; low input dominant driver; internal pull?up current 2 gnd ground 3 v cc supply voltage 4 rxd receive data output; dominant transmitter low output 5 5 v io v split input/output pins supply voltage. on ncv7342?3 only common?mode stabilization output. on ncv7342?0 only 6 canl low?level can bus line (low in dominant mode) 7 canh high?level can bus line (high in dominant mode) 8 stb standby mode control input ep exposed pad connect to gnd or left floating
ncv7342 www. onsemi.com 6 functional description ncv7342 has two versions which differ from each other only by function of pin 5. ncv7342?0 : pin 5 is common mode stabilization output v split . (see figure 4) this version is full replacement of ncv7340. ncv7342?3 : pin 5 is v io pin, which is supply pin for transceiver digital inputs/output (supplying pins txd, rxd, stb) the v io pin should be connected to microcontroller supply pin. by using v io supply pin shared with microcontroller, the i/o levels between microcontroller and transceiver are properly adjusted. this adjustment allows communication between 3 v microcontroller and the transceiver. (see figure 3) operating modes ncv7342 provides two modes of operation as illustrated in table 3. these modes are selectable through pin stb. table 3. operating modes pin stb mode pin rxd low high low normal bus dominant bus recessive high standby wake?up request detected no wake?up request detected normal mode in normal mode, the transceiver is able to communicate via the bus lines. the signals are transmitted and received to the can controller via the pins txd and rxd. the slopes on the bus lines outputs are optimized to give extremely low eme. standby mode in standby mode both the transmitter and receiver are disabled and a very low?power differential receiver monitors the bus lines for can bus activity. the bus lines are terminated to ground and supply current is reduced to a minimum, typically 10 a. when a wake?up request is detected by the low?power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of t dwakerd . the rxd pin is driven low by the transceiver to inform the controller of the wake?up request. v io supply pin the v io pin (available only on ncv7342?3 version) should be connected to microcontroller supply pin. by using v io supply pin shared with microcontroller the i/o levels between microcontroller and transceiver are properly adjusted. see figure 3. pin v io also provides the internal supply voltage for low?power differential receiver of the transceiver. this allows detection of wake?up request even when there is no supply voltage on pin v cc . split circuit the v split pin (available on ncv7342?0 version) is operational only in normal mode. in standby mode this pin is floating. the v split can be connected as shown in figure 4 or, if it?s not used, can be left floating. its purpose is to provide a stabilized dc voltage of 0.5 v cc to the bus reducing possible steps in the common?mode signal, therefore reducing eme. these unwanted steps could be caused by an unpowered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal 0.5 v cc voltage. wake?up when a valid wake?up (dominant state longer than t wake ) is received during the standby mode, the rxd pin is driven low after t dwakerd . the wake?up detection is not latched: rxd returns to high state after t dwakedr when the bus signal is released back to recessive ? see figure 5. canh canl stb rxd1 time normal standby figure 5. ncv7342 wake?up behavior >t wake ncv7342 www. onsemi.com 7 over?temperature detection a thermal protection circuit protects the ic from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 180 c. because the transmitter dissipates most of the power, the power dissipation and temperature of the ic is reduced. all other ic functions continue to operate. the transmitter of f?state resets when the temperature decreases below the shutdown threshold and pin txd goes high. the thermal protection circuit is particularly needed in case of a bus line failure. txd dominant time?out function a txd dominant time?out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication), if pin txd is forced permanently low by a hardware and/or software application failure. the timer is triggered by a negative edge on pin txd. if the duration of the low?level on pin txd exceeds the internal timer value t dom(txd) , the transmitter is disabled, driving the bus into a recessive state. the timer is reset by a positive edge on pin txd. this txd dominant time?out time (t dom(txd) ) limits the minimum possible bit rate to 8 kbps. bus dominant time?out function bus dominant time?out timer is started in the standby mode when can bus changes from recessive to dominant state. if the dominant state on the bus is kept for longer time than t dom(bus) , the rxd pin is released to high level. the timer is reset when can bus changes from dominant to recessive state. this feature prevents generating permanent wake?up request by the bus clamped to the dominant level. fail safe features a current?limiting circuit protects the transmitter output stage from damage caused by an accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. v cc supply dropping below v uvvcc undervoltage level will force transceiver to switch into the standby mode. the logic level on pin stb will be ignored as long as undervoltage condition is not recovered. (ncv7342?3 version only) v io supply dropping below v uvdvio undervoltage detection level will cause the transceiver to disengage from the bus (no bus loading) until the v io voltage recovers. (ncv7342?3 version only) the pins canh and canl are protected against automotive electrical transients (according to iso 7637; see figure 6). pins txd and stb are pulled high internally should the input become disconnected. pins txd, stb and rxd will be floating, preventing reverse supply should the v cc supply be removed.
ncv7342 www. onsemi.com 8 electrical characteristics definitions all voltages are referenced to gnd (pin 2). positive currents flow into the ic. sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. table 4. absolute maximum ratings symbol parameter conditions min max unit v sup supply voltage v cc , v io ?0.3 +6 v v canh dc voltage at pin canh 0 < v cc < 5.5 v; no time limit ?50 +50 v v canl dc voltage at pin canl 0 < v cc < 5.5 v; no time limit ?50 +50 v v canh,lmax dc voltage at pin canh and canl during load dump condition 0 < v cc < 5.5 v; less than one second ? 58 v v split dc voltage at v split pin (on ncv7342?0 version only) 0 < v cc < 5.5 v; no time limit ?50 +50 v v io dc voltage at pin txd, rxd, stb ?0.3 +6 v v esd electrostatic discharge voltage at all pins according to eia?jesd22 (note 2) ?4 +4 kv standardized charged device model esd pulses according to esd?stm5.3.1?1999 ?750 +750 v electrostatic discharge voltage at canh,canl, v split pins according to eia?jesd22 (note 2) ?8 +8 kv electrostatic discharge voltage at canh , canl pins according to iec 61000?4?2 (note 3) ?15 +15 kv v schaff transient voltage at canh, canl pins, see figure 6 (note 4) ?150 +100 v latch?up static latch?up at all pins (note 5) 15 0 ma t stg storage temperature ?55 +150 c t amb ambient temperature ?40 +125 c t j maximum junction temperature ?40 +170 c msl moisture sensitivity level soic 2 ? msl moisture sensitivity level dfn 1 ? t sld lead temperature soldering reflow (smd styles only), pb?free versions (note 6) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 2. standardized human body model electrostatic discharge (esd) pulses in accordance to eia?jesd22. equivalent to discharging a 1 00 pf capacitor through a 1.5 k resistor. 3. system human body model electrostatic discharge (esd) pulses. equivalent to discharging a 150 pf capacitor through a 330 resistor referenced to gnd. verified by external test house 4. pulses 1, 2a,3a and 3b according to iso 7637 part 3. verification by external test house. 5. static latch?up immunity: static latch?up protection level when tested according to eia/jesd78. 6. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d table 5. thermal characteristics rating symbol value unit thermal characteristics, soic?8 (note 7) thermal resistance, junction?to?air, free air, 1s0p pcb (note 8) thermal resistance, junction?to?air, free air, 2s2p pcb (note 9) r ja r ja 125 75 c/w c/w thermal characteristics, dfn?8, 3x3 mm (note 7) thermal resistance, junction?to?air, free air, 1s0p pcb (note 8) thermal resistance, junction?to?air, free air, 2s2p pcb (note 9) r ja r ja 140 47 c/w c/w 7. refer to electrical characteristics, recommended operating ranges and/or application information for safe operating parameters. 8. values based on test board according to eia/jedec standard jesd51?3, signal layer with 10% trace coverage. 9. values based on test board according to eia/jedec standard jesd51?7, signal layers with 10% trace coverage for the signal lay er and 4 thermal vias connected between exposed pad and first inner cu layer.
ncv7342 www. onsemi.com 9 table 6. characteristics v cc = 4.5 v to 5.5 v; v io = 2.8v to 5.5 v (note 10); t j = ?40 to +150 c; r lt = 60 unless specified otherwise. on chip versions without v io pin reference voltage for all digital inputs and outputs is v cc instead of v io . symbol parameter conditions min typ max unit supply (pin v cc ) i cc supply current dominant; v txd = 0 v recessive; v txd = v io 50 6.8 75 10 ma i ccs 0 supply current in standby mode for ncv7342?0 t j 100 c (note 11) 8 15 a i ccs3 supply current in standby mode for ncv7342?3 including current into v io t j 100 c (note 11) 17 a v uvvcc undervoltage detection voltage on v cc pin (ncv7342?3 only) 3.5 4.5 v transmitter data input (pin txd) v ih high?level input voltage output recessive 2.0 6 v v il low?level input voltage output dominant ?0.3 +0.8 v i ih high?level input current v txd = v io ?5 0 +5 a i il low?level input current v txd = 0v ?385 ?200 ?45 a c i input capacitance not tested 5 10 pf transmitter mode select (pin stb) v ih high?level input voltage standby mode 2.0 v io +0.3 (note 12) v v il low?level input voltage normal mode ?0.3 +0.8 v i ih high?level input current v stb = v io ?5 0 +5 a i il low?level input current v stb = 0 v ?10 ?4 ?1 a c i input capacitance not tested 5 10 pf receiver data output (pin rxd) i oh high?level output current normal mode v rxd = v io ? 0.4 v ?1.2 ?0.4 ? 0. 1 ma i ol low?level output current v rxd = 0.4 v 1.5 6 12 ma v oh high?level output voltage standby mode i rxd = ?100 a v io ? 1.1 v io ?0.7 v io ? 0.4 v bus lines (pins canh and canl) v o(reces) (norm) recessive bus voltage on pins canh and canl v txd = v io ; no load; normal mode 2.0 2.5 3.0 v v o(reces) (stby) recessive bus voltage on pins canh and canl v txd = v io ; no load; standby mode ?100 0 +100 mv i o(reces) (canh) recessive output current at pin canh ?30 v < v canh < 35 v; 0 v < v cc < 5.5 v ?2.5 +2.5 ma i o(reces) (canl) recessive output current at pin canl ?30 v < v canl < 35 v; 0 v v cc , the limit is v io + 0.3 v
ncv7342 www. onsemi.com 10 table 6. characteristics v cc = 4.5 v to 5.5 v; v io = 2.8v to 5.5 v (note 10); t j = ?40 to +150 c; r lt = 60 unless specified otherwise. on chip versions without v io pin reference voltage for all digital inputs and outputs is v cc instead of v io . symbol unit max typ min conditions parameter bus lines (pins canh and canl) v o(dom) (canl) dominant output voltage at pin canl v txd = 0 v 0.5 1.4 1.75 v v o(dif) (bus_dom) differential bus output voltage (v canh ? v canl ) v txd = 0 v; dominant; 45 < r lt < 65 1.5 2.25 3.0 v v o(dif) (bus_rec) differential bus output voltage (v canh ? v canl ) v txd = v io ; recessive; no load ?120 0 +50 mv v o(sym) (bus_dom) bus output voltage symmetry v canh + v canl v txd = 0 v 0.9 1.1 v cc i o(sc) (canh) short circuit output current at pin canh v canh = 0 v; v txd = 0 v ?9 0 ?70 ?40 ma i o(sc) (canl) short circuit output current at pin canl v canl = 36 v; v txd = 0 v 40 70 100 ma v i(dif) (th) differential receiver threshold voltage ?12 v < v canl < 12 v; ?12 v < v canh < 12 v; v cc = 4.75 v to 5.25 v 0.5 0.7 0.9 v v ihcm(dif) (th) differential receiver threshold voltage for high common?mode ?30 v < v canl < 35 v; ?30 v < v canh < 35 v; v cc = 4.75 v to 5.25 v 0.40 0.7 1.0 v v i(dif) (th)_stdby differential receiver threshold voltage in standby mode ?12 v < v canl < 12 v; ?12 v < v canh < 12 v; v cc = 4.5 v to 5.5 v 0.4 0.8 1.15 v r i(cm) (canh) common?mode input resistance at pin canh 15 26 37 k r i(cm) (canl) common?mode input resistance at pin canl 15 26 37 k r i(cm) (m) matching between pin canh and pin canl common mode input resistance v canh = v canl ?0.8 0 +0.8 % r i(dif) differential input resistance 25 50 75 k c i(canh) input capacitance at pin canh v txd = v io ; not tested 7.5 20 pf c i(canl) input capacitance at pin canl v txd = v io ; not tested 7.5 20 pf c i(dif) differential input capacitance v txd = v io ; not tested 3.75 10 pf common?mode stabilization (pin v split ) only for ncv7342?0 version v split reference output voltage at pin v split normal mode; ?500 a < i split < 500 a 0.3 0.7 v cc v splito reference output voltage at pin v split r loadvsplit > 1 m 0.45 0.55 v cc i split(i) v split leakage current standby mode ?5 +5 a i split(lim) v split limitation current normal mode 1.3 5 ma v io supply voltage (pin v io ) only for ncv7342?3 version v io supply voltage on pin v io 2.8 5.5 v i ios supply current on pin v io in standby mode t j 100 c (note 11) 14 a 10. only version ncv7342?3 has v io supply pin. in ncv7342?0 this supply is provided from v cc pin. 11. not tested in production. guaranteed by design and prototype evaluation. 12. in case v io > v cc , the limit is v io + 0.3 v
ncv7342 www. onsemi.com 11 table 6. characteristics v cc = 4.5 v to 5.5 v; v io = 2.8v to 5.5 v (note 10); t j = ?40 to +150 c; r lt = 60 unless specified otherwise. on chip versions without v io pin reference voltage for all digital inputs and outputs is v cc instead of v io . symbol unit max typ min conditions parameter v io supply voltage (pin v io ) only for ncv7342?3 version i ionm supply current on pin v io normal mode dominant; v txd = 0 v recessive; v txd = v io 0.30 0.29 0.70 0.44 1.10 0.68 ma v uvdvio undervoltage detection voltage on v io pin 1.3 2.7 v thermal shutdown t j(sd) shutdown junction temperature junction temperature rising 160 180 200 c timing characteristics (see figure 7 and 8) t d(txd?buson) delay txd to bus active c i = 100 pf between canh to canl 60 ns t d(txd?busoff) delay txd to bus inactive c i = 100 pf between canh to canl 30 ns t d(buson?rxd) delay bus active to rxd c rxd = 15 pf 60 ns t d(busoff?rxd) delay bus inactive to rxd c rxd = 15 pf 70 ns t pd_dr propagation delay txd to rxd dominant to recessive transition see figure 8 c i = 100 pf between canh to canl, c rxd = 15 pf 50 100 230 ns t pd_rd propagation delay txd to rxd recessive to dominant transition see figure 8 c i = 100 pf between canh to canl, c rxd = 15 pf 50 120 230 ns t d(stb?nm) delay standby mode to normal mode 47 s t wake dominant time for wake?up via bus 0.5 2.1 5 s t dwakerd delay to flag wake event (recessive to dominant transitions) see figure 5 valid bus wake?up event, c rxd = 15 pf 1 3.5 10 s t dwakedr delay to flag end of wake event (dominant to recessive transition) see figure 5 valid bus wake?up event, c rxd = 15 pf 0.5 2.6 6 s t wake(rxd) minimum pulse width on rxd see figure 5 5 s t wake c rxd = 15 pf 0.5 s t dom(txd) txd dominant time for time out v txd = 0 v 1.3 5 ms t dom(bus) bus dominant time out standby mode 1.3 5 ms 10. only version ncv7342?3 has v io supply pin. in ncv7342?0 this supply is provided from v cc pin. 11. not tested in production. guaranteed by design and prototype evaluation. 12. in case v io > v cc , the limit is v io + 0.3 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncv7342 www. onsemi.com 12 measurement set?ups and definitions ncv7342 gnd 2 3 canh canl 5 6 7 stb 8 rxd 4 txd 1 1 nf 100 nf + 1 nf transient generator rb20121608 15 pf 5v figure 6. test circuit for automotive transients 8 ncv7342 gnd 2 3 canh canl 5 6 7 stb rxd 4 txd 1 100 nf +5 v 47 uf 100 pf rb20120816 15 pf r l figure 7. test circuit for timing characteristics v cc v io v cc v io
ncv7342 www. onsemi.com 13 dominant 0.9 v 0.5 v recessive 50% recessive 50% txd canh canl rxd rb20130429 0.7 x v cc * 0.3 x v cc * t d(busoff?rxd) t d(buson?rxd) t d(txd?busoff) t d(txd?buson) v i(dif) = v canh ? v canl *on ncv7342?3 v cc is replaced by v io figure 8. transceiver timing diagram t pd_rd t pd_dr device ordering information part number description package shipping ? ncv7342d10r2g high speed can transceiver with standby and v split pin soic 150 8 green (matte sn, jedec ms?012) (pb?free) 3000 / tape & reel ncv7342d13r2g high speed can transceiver with standby and v io pin ncv7342mw3r2g high speed can transceiver with standby and v io pin dfn 8 wettable flank (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv7342 www. onsemi.com 14 package dimensions soic?8 case 751az issue b 7.00 8x 0.76 8x 1.52 1.27 dimensions: millimeters 1 pitch *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* recommended notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.004 mm in excess of maximum material condition. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006 mm per side. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.010 mm per side. 5. the package top may be smaller than the package bot- tom. dimensions d and e1 are determined at the outer- most extremes of the plastic body at datum h. 6. dimensions a and b are to be determined at datum h. 7. dimensions b and c apply to the flat section of the lead between 0.10 to 0.25 from the lead tip. 8. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. 14 85 seating plane detail a 0.10 c a1 dim min max millimeters h 0.25 0.41 a --- 1.75 b 0.31 0.51 l 0.40 1.27 e 1.27 bsc c 0.10 0.25 a1 0.10 0.25 l2 m 0.25 a-b b 8x c d a b c top view side view 0.25 bsc e1 3.90 bsc e 6.00 bsc d e d 0.20 c 0.10 c 2x note 6 notes 4&5 notes 4&5 side view end view e e1 d 0.10 c d d notes 3&7 note 6 note 8 a a2 a2 1.25 --- d 4.90 bsc h seating plane detail a l c l2 h 45 chamfer c note 7
ncv7342 www. onsemi.com 15 package dimensions dfn8, 3x3, 0.65p case 506cs issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. a b e d d2 e2 bottom view b e 8x 0.10 b 0.05 a c c note 3 2x 0.10 c pin one reference top view 2x 0.10 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l 8x 14 5 8 dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 3.00 bsc d2 2.30 2.50 e 3.00 bsc e2 1.50 1.70 e 0.65 bsc l 0.30 0.40 ?? ?? ? ? ? ? ?? ?? ?? ?? ? ? ? ? ?? ?? 1 0.65 pitch 3.30 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 8x dimensions: millimeters l1 detail a l alternate terminal constructions l detail b detail a l1 0.00 0.15 note 4 e/2 soldering footprint* ??? ??? ?? on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv7342/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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